1. Field of Use
This invention relates to data processing systems and more specifically to bus systems.
2. Prior Art
In general, when different sources share a common bus, care must be taken to ensure a smooth transition from one user to the other. In asynchronous bus systems, users gain access through the use of a priority resolution or arbitration networks. In such cases, the resolution or arbitration is completed during a previous cycle and the user designated as having been granted access, is allowed bus use for the next bus cycle.
In synchronous bus systems, such as that utilized with the Intel 486.sup.tm microprocessor, asserting a bus hold request (HOLD) input indicates that another bus master user desires control of the microprocessor's bus. The microprocessor responds by floating its bus and driving a bus hold acknowledge (HLDA) output lead to an active state, after completing the current bus cycle, burst cycle or sequence of locked cycles.
The microprocessor will remain in this state until HOLD is deasserted by the non-microprocessor user. Generally, the user bus master bus control circuits are clocked between the same edges of the basic clock signal provided by the system clock. However, if too little time is allowed for the bus transition, the bus master tristate circuit outputs can overlap, resulting in possible erroneous operations. If too much time allowed for the bus transition, system performance will suffer.
In order to avoid the tristate overlap problem described above, it becomes necessary to move out the bus enable of the other non-microprocessor bus master to coincide with a clock edge which guarantees no tristate overlap. In this case, on the first clock edge, the non-microprocessor bus master user requests use of the bus by asserting the HOLD input and on a second clock edge, the microprocessor can acknowledge the request by by forcing the HLDA output active and releasing its address bus. On a third clock edge, the non-microprocessor bus master is able to place its address onto the microprocessor bus and then on a fourth clock edge, a bus slave receiving unit can strobe or receive the address placed on the microprocessor bus.
While this scheme provides a high level performance, it becomes desirable to have a minimum time between transitions, particularly where there is a requirement for more switching between microprocessor and non-microprocessor bus users.
Accordingly, it is a primary object of the present invention to provide a bus access arrangement in which a minimum amount of time is required for transitions between different bus users.